1. Field of the Invention
The present invention relates to a microelectronic packaging module utilizing single layer ceramic, individually hermetically sealed chip packages upon a pair of printed circuit boards mounted back to back. This multi-chip package approach facilitates high density packaging utilizing existing military standard formats via lightweight replaceable modules having low capacitance and low power dissipations. These modules are operable to function at high clock speeds, and are particularly suited in VHSIC (very high speed integrated circuit) opertions.
2. Description of the Prior Art
A multi-chip hybrid is usually considered a hermetically sealed enclosure having a multiplicity of bare active chips and other devices incorporated within. The problems associated with building hybrids are accepted in return for the advantage of the increased packaging density. This increase in packaging density, however, does not come about with all hybrids. Other assumptions with hybrid packaging are that:
(1) the hybrid will have a small number of input/output pins compared to the total number of bonding pads on the chips inside the hybrid, and
(2) that the chips in a given circuit can be partitioned electrically and mechanically into hybrid packages such that most of the connections are made between the chips within a given hybrid and a smaller number of connections are made from one hybrid to another hybrid or from one hybrid to other single chip packages.
While these two assumptions may be true, in some cases they are not always true, especially in large circuits which require a significant number of high density, high speed gate arrays. If a large number of gate array chips is partitioned into a small number of hybrid packages, for example, 32 gate array chips partitioned into 4 hybrid packages, as many as 80 to 90% of the chips' input/output connections might have to come out of the hybrid packages.
Each chip could require connection to every other chip in the circuit as much or almost as much as it was connected to the other chips in the same hybrid package. These 8 chip hybrids would require in the neighborhood of 1,000 pins which would significantly detract from the hybrid's use and appeal. A similar situation would exist if a given module were to be divided in half and packaged in two modules. There would still be an excessively large number of connector pins required to connect the two modules together.
In addition to electrical partitioning problems, there are mechanical layout problems associated with hybrid packages in light of the small SEM (standard electronic module) size modules that are now required in military use. The largest of these standard sizes permits 5.times.5 inches of circuit board area upon which to place all of the utilizable components. A multi-chip hybrid would represent a significant fraction of that total amount of board area. In the layout of a relatively small board having large hybrids, there is a high probability of not being able to use all of the available board space unless a standard hybrid size were developed so that a predetermined number of hybrids would exactly cover all the available SEM board area.
For example, 4 hybrids each occupying 21/2.times.21/2 inches would completely cover the area. With the SEM size established and the hybrid size established then the problem becomes one of partitioning the circuit in such a way that all of the space inside the hybrids would be used and that the pin-out requirements between the hybrids would be met. This is the same problem as fitting arbitrarily sized hybrids upon the SEM format. A risk exists inside the hybrid of not utilizing all of the hybrid area and of requiring too many input/output pins between the hybrids. An alternative method of utilizing a given amount of area is to fill it with a large number of small packages rather than a small number of large packages. One way to do this is to define the SEM module size as the hybrid size and build a large 5.times.5 inch hermetically sealed bare chip hybrid having a connector at one edge and calling this a standard electronic module (SEM).
The drawbacks to the large hybrid approach would be the risk associated with the hermetic sealing, unsealing and resealing of such large modules to make the inevitable bare chip replacements. It is not possible to thoroughly screen and burn-in bare chips. This module would, therefore, receive a large number of bare chip replacements.
In the prior art, packaging for a high speed chip having a plurality of contact pads and comprising a carrier and cover has been developed in utilizing multi-layer ceramic. This carrier would be formed of a base of insulating material having a generally planar area for receiving the chip. A cooling stud is mounted on the base and provided with one or more removable cooling fins. This stud, for example, would be mounted on the base under the area for receipt of the chip. Spaced leads would be carried by the base and have outer extremities which extended beyond the base in a direction away from the chip free from the carrier and having inner extremities which are in close proximity to the area for receiving the chip. A grounding bus would be carried by the carrier for the electrical checking of the package. This multi-layer ceramic co-fired structure resulting from the stack and firing at high temperatures of multiple layers of ceramic material was described in U.S. Pat. No. 3,872,583 dated Mar. 25, 1975. Inventors Robert J. Beall and John J. Zasio in their patent entitled "LSI Chip Package and Method" describe this multi-layer ceramic package.
The problem to be solved then is the design and fabrication of a high density microelectronic packaging module operable to provide high density packaging on a variety of module formats including the relatively small standard military formats. Further, this same module would require high clock speed and low power dissipation requires an interconnect structure having these conductors supported by a low dielectric constant material. This packaging module should allow pretest of the bread board and burn-in of the individual integrated circuit devices before commitment to the final assembly. This module would also have a short design cycle approach which inherently allows for timely insertion of high speed technology as it becomes available.